1. Field
This patent document relates to a semiconductor design technology, and more particularly, to a semiconductor memory device which performs a refresh operation.
2. Description of the Related Art
Semiconductor memory devices such as DRAM include memory banks for storing data, and each of the memory banks includes a large number of memory cells. Each of the memory cells includes a cell transistor serving as a switch and a cell capacitor for storing data. Since leakage of current occurs due to the memory cell structure, particularly in the PN junction of the cell transistor, data stored in the cell capacitor may be lost. Therefore, semiconductor memory devices require refresh operations of recharging the memory cells before data is lost (hereafter, referred to as a ‘normal refresh operation’).
A normal refresh operation may include an auto refresh operation and a self refresh operation. An auto refresh operation occurs in response to a refresh command applied from outside (i.e. an external source), and a self-refresh operation occurs when the semiconductor memory device changes an internal address in response to a refresh command applied from outside.
In addition to normal refresh operations, a semiconductor memory device may perform an additional refresh operation on memory cells coupled to a word line that is likely to lose data due to row hammering. Row hammering is a phenomenon in which data of a memory cell is lost due to repeated activations of adjacent word lines. In order to prevent loss of data from row hammering, an additional refresh operation is performed on word lines that are activated a predetermined number of times or more. This operation is typically referred to as a target-row refresh (TRR) operation.
The TRR operation is divided into a single bank refresh operation and an all bank refresh operation. The single bank refresh operation refers to when only one bank is refreshed, and the all bank refresh operation refers to when all the banks are refreshed.
During an all bank refresh operation, target row addresses for all of the banks are output. As a target-row refresh (TRR) signal is activated during the all bank refresh operation, the semiconductor memory device may activate an output control signal for controlling the output timing of a target row address of a first bank. Then, the semiconductor memory device may shift the output control signal of the first bank and sequentially activate output control signals of the other banks to perform the TRR operation on all of the banks.
During a single bank refresh operation, the semiconductor memory device performs a refresh operation whenever a single bank refresh command containing specific bank information is applied from outside. The single bank refresh operation is also referred to as a per bank refresh operation.
During a conventional single bank refresh operation, the semiconductor memory device may generate a short pulse in response to the single bank refresh command containing the bank information. Thus, the semiconductor memory device may output a target row address of the corresponding bank and perform the TRR operation.
However, when the single bank refresh operation is performed through the above-described method, the single bank refresh operation and the all bank refresh operation may overlap since the TRR signal activated during the all bank refresh operation is the same signal as the TRR signal activated during the single bank refresh operation. Thus, although the single bank refresh operation is performed in response to the single bank refresh command applied from outside, the output control signal of the first bank, which is activated during the all bank refresh operation, may be automatically activated. In this case, the single bank refresh operation and the all bank refresh operation may overlap. Therefore, the semiconductor memory device may have difficulty in normally performing the single bank refresh operation.